Many of today's computer systems are implemented using multiprocessor architectures. In such systems, multiple processing resources, such as multiple processor sockets may be present. Each socket may include one or more processor cores and cache memories, among other such components. While such systems can provide high throughput computing performance, their design includes challenges and can lead to tradeoffs that may impact performance.
For example, multiple processing resources within a single system may desire to access the same data at approximately the same time. To enable improved performance, multiple processors may store a data item in closer relation to it than a mass storage location where the data item may be located. Accordingly, many processors include cache memory to improve the performance of the processor, typically by reducing memory access latency. Processing devices that use multiple cache memory modules, such as multi-core processors, typically implement one or more techniques to maintain cache coherency. In some circumstances because of circular dependencies that may be created due to certain microarchitectural implementations in a multiprocessor system, coherency protocols can result in deadlock conditions. Such conditions prevent forward progress and can cause system hangs, reducing system performance.